Heterogeneous Power Delivery for 7nm High-Performance Chiplet-Based Processors using Integrated Passive Device and In-Package Voltage Regulator

• Published in: 2020 IEEE Symposium on VLSI Technology pp. 1 - 2
• Main Authors: Roth, Alan, Zhou, Charlie, Wong, Mei, Soenen, Eric, Huang, Tze-Chiang, Ranucci, Paul, Hsu, Ying-Chih, Lin, Hung-Chih, Kuo, Chester, Wang, Min-Jer, Yang, Sheng-Yao, Chu, J. R., Yeh, Ting-Yu, Ting, K. C., Loke, Alvin L. S., Rusu, Stefan, Chen, Mark, Lee, Frank Y. H., Zhang, Kevin, Kalnitsky, Alex
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-06-2020
• Subjects: Capacitors; Inductors; Load modeling; Program processors; Regulators; Very large scale integration; Voltage control
• ISSN: 2158-9682
• DOI: 10.1109/VLSITechnology18217.2020.9265105

We demonstrate two heterogeneous solutions to improve power delivery to High-Performance Computing (HPC) processors. The scalable HPC vehicle integrates two 7nm CMOS processor chiplets, each with four ARM ® Cortex ® -A72 cores, that are mounted on a Chip-on-Wafer-on-Substrate (CoWoS ® ) silicon interposer [1]. In the first solution, Integrated Passive Device (IPD) capacitors are placed directly beneath the interposer to provide more accessible and effective supply noise decoupling. The result is 3.9% higher maximum clock frequency at a core supply of 1.135V. In the second solution, the processor is powered by a laterally mounted in-Package Voltage Regulator (PVR) built in 28nm CMOS augmented with high-per-meability on-die inductors. The processor performance provided by the buck converter-based PVR matches that by an off-package External Voltage Regulator (EVR). As processor power increases with higher core counts, PVRs with on-die inductors will be increasingly compelling for efficient system power delivery.