Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training

Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training

This article presents methods of increasing logic built-in self-test (LBIST) delay fault coverage using artificial neural networks (ANNs) to selecting test point (TP) locations a method to train ANNs using randomly generated circuits. This method increases delay test quality both during and after ma...

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Bibliographic Details
Published in:2019 IEEE 28th Asian Test Symposium (ATS) pp. 13 - 135
Main Authors: Millican, Spencer, Sun, Yang, Roy, Soham, Agrawal, Vishwani
Format: Conference Proceeding
Language:English
Published: IEEE 01-12-2019
Subjects:
Artificial neural networks
Circuit faults
Delays
intellectual property
lbist
Logic gates
neural networks
Neurons
test points
Training
Training data
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Summary:This article presents methods of increasing logic built-in self-test (LBIST) delay fault coverage using artificial neural networks (ANNs) to selecting test point (TP) locations a method to train ANNs using randomly generated circuits. This method increases delay test quality both during and after manufacturing. This article also trains ANNs without relying on valuable third-party intellectual property (IP) circuits. Results show higher-quality TPs are selected in significantly reduced CPU time and third-party IP is not be required for ANN training.
ISSN:2377-5386
DOI:10.1109/ATS47505.2019.000-7