Quantitative 3-D Model to Explain Large Single Trap Charge Variability in Vertical NAND Memory

We present a TCAD model that reproduces large single trap V T -shifts (>100mV) in 3-D NAND flash read current by means of targeted charge placement based on linear response. With this model, we investigate worst-case V T -shifts in terms of bias conditions and junction position, showing low local...

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Bibliographic Details
Published in:	2019 IEEE International Electron Devices Meeting (IEDM) pp. 32.1.1 - 32.1.4
Main Authors:	Verreck, D., Furnemont, A., Arreghini, A., Bastos, J.P., Schanovsky, F., Mitterbauer, F., Kernstock, C., Karner, M., Degraeve, R., den bosch, G. Van
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-12-2019
Online Access:	Get full text
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Summary:	We present a TCAD model that reproduces large single trap V T -shifts (>100mV) in 3-D NAND flash read current by means of targeted charge placement based on linear response. With this model, we investigate worst-case V T -shifts in terms of bias conditions and junction position, showing low local carrier density at the origin of large shifts. We outline a sampling strategy that allows to reproduce experimental distributions for realistic grain size (12nm) and highlight the role of transconductance to explain anomalous large shifts.
ISSN:	2156-017X
DOI:	10.1109/IEDM19573.2019.8993552