FETs on 2-D Materials: Deconvolution of the Channel and Contact Characteristics by Four-Terminal Resistance Measurements on WSe2 Transistors

• Published in: IEEE transactions on electron devices Vol. 64; no. 7; pp. 2970 - 2976
• Main Authors: Sutar, Surajit, Asselberghs, Inge, Lin, Dennis H. C., Thean, Aaron Voon-Yew, Radu, Iuliana
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-07-2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 2-D materials; Asymmetry; Bias; Contact resistance; Deconvolution; Dielectric strength; Doping; Electrical resistance measurement; Encapsulation; FET contact resistance; Logic gates; Metals; MOSFET; MOSFET contact resistance; MX2; Polarity; Resistance; Semiconductor devices; Transistors; transition metal dichalcogenide (TMDC); WSe
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2017.2698601

FETs made on 2-D semiconductors, typically without degenerate doping at the contacts, have a significant Schottky junction (SJ) resistance, which complicates transistor analysis. This paper evaluates the effect of the contact resistance on the 2-D-material FET characteristics through four-terminal (4-T) resistance measurements on WSe 2 FETs, which allow studying the channel and contacts characteristics separately. Apart from showing the nonnegligibility of contact resistance, this paper enables a finer understanding of commonly observed phenomena, such as transistor performance improvement with dielectric-encapsulation is observed to have a stronger effect on the contact than the channel; the resistance of the forward-biased SJ is observed to be not negligible, but comparable to that of the reverse-biased junction; at biases commonly referred to as "low-bias," the WSe 2 FET resistance could be dominated by the contacts; and pinchoff can be observed at relatively lower current levels, being related to the channel-contact resistance ratio rather than their magnitudes. In the devices where true channel pinchoff can be verified, a correlation emerges between current saturating behavior and asymmetry in the output characteristics with respect to the drain-source bias polarity, a feature that may serve as a guide toward interpreting standard FET output characteristics in 2-D materials.