5.75 to 44Gb/s quarter rate CDR with data rate selection in 90nm bulk CMOS

• Published in: ESSCIRC 2008 - 34th European Solid-State Circuits Conference pp. 166 - 169
• Main Authors: von Bueren, G., Rodoni, L., Jaeckel, H., Huber, A., Brun, R., Holzer, D., Schmatz, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2008
• Subjects: Bit error rate; clock data recovery; Clocks; CMOS; CMOS logic circuits; CMOS process; CMOS technology; Digital filters; Energy consumption; Frequency; Laboratories; quarter rate; Tracking loops
• ISBN: 9781424423613; 1424423619
• ISSN: 1930-8833; 2643-1319
• DOI: 10.1109/ESSCIRC.2008.4681818

This paper presents a quarter rate clock/data recovery (CDR) circuit for plesiochronous serial I/O-links. This 2x-oversampled phase-tracking CDR, implemented in 90 nm bulk CMOS technology, covers the whole range of data rates from 5.75 to 44 Gb/s thanks to a data rate selection logic. A bit error rate <10 -12 was verified up to 38 Gb/s using a 2 7-1 PRBS pattern. The CDR is able to track a maximum frequency deviation of plusmn615 ppm between incoming data and reference clock.