Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation

• Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1 - 5
• Main Authors: Oyeniran, Adeboye Stephen, Azad, Siavoosh Payandeh, Ubar, Raimund
• Format: Conference Proceeding
• Language: English
• Published: IEEE 27-05-2018
• Subjects: Adders; Built-in self-test; Circuit faults; Computer architecture; Hardware; Microprocessors
• ISSN: 2379-447X
• DOI: 10.1109/ISCAS.2018.8350936

This paper presents a new method for pseudo-exhaustive testing of standard array multipliers using a novel approach of data-controlled segmentation of the circuit. The method covers both combinational and sequential fault classes. Differently from previous papers, the proposed separate cell-testing approach targets multiple faults in different cells and avoids fault masking. The method is also applicable to other multiplier architectures like Booth and MiniMIPS with high stuck-at fault (SAF) coverage. The regular structure of the test allows efficient implementation of the method as both software based self-test (SBST) and hardware-based BIST.