Degradation behaviour of polysilicon high voltage thin film transistors

• Published in: Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614) pp. 219 - 222
• Main Authors: Mugnier, M., Manhas, S.K., Chandra Sekhar, D., Krishnan, S., Cross, R., Sankara Narayanan, E.M., De Souza, M.M., Flores, D., Vellvehi, M., Millan, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2002
• Subjects: Active matrix liquid crystal displays; Annealing; Degradation; Glass; Low voltage; Silicon; Stress; Temperature; Thin film transistors; Threshold voltage
• ISBN: 9780780374164; 0780374169
• DOI: 10.1109/IPFA.2002.1025666

The degradation characteristics of polycrystalline silicon Off-set Drain High Voltage Thin Film Transistors (OD-HVTFTs) are reported. The results demonstrate a pronounced kink in the transfer characteristics at high gate bias, due to degradation of the offset region. This effect is particularly noticeable in non-hydrogenated HVTFTs. Annealing of devices in atmospheric ambient after stress shows temperature dependent recovery.