BIST-aided scan test - a new method for test cost reduction

• Published in: Proceedings. 21st VLSI Test Symposium, 2003 pp. 359 - 364
• Main Authors: Hiraide, T., Kwame Osei Boateng, Konishi, H., Itaya, K., Emori, M., Yamanaka, H., Mochiyama, T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2003
• Subjects: Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Integrated circuit testing; Laboratories; Large scale integration; Logic testing
• ISBN: 9780769519241; 0769519245
• ISSN: 1093-0167; 2375-1053
• DOI: 10.1109/VTEST.2003.1197675

It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increase in test cost is caused in accordance with increasing design complexity. Recent strategies for test cost reduction combine ATPG and BIST techniques. Unfortunately, these strategies have serious constraints. We propose a new method that employs ATE and BIST structures to apply coded test patterns to LSI circuits. Results obtained using practical circuits show drastic test cost reduction capability of the proposed method.