An amalgamation of hardening methods for single event upset mitigation in memory elements

An amalgamation of hardening methods for single event upset mitigation in memory elements

A modification of the Muller C-Element is proposed as a single event transient (SET) and single event upset (SEU) mitigation circuit. Proton tests suggests its efficiency compared to unmitigated designs.

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Bibliographic Details
Published in:2016 16th European Conference on Radiation and Its Effects on Components and Systems (RADECS) pp. 1 - 4
Main Authors: Smith, Farouk, Gaffoor, Shaaista
Format: Conference Proceeding
Language:English
Published: IEEE 01-09-2016
Subjects:
Delays
Field programmable gate arrays
Latches
Logic gates
multiple cell upset (MCU)
Redundancy
Single event transient (SET)
single event upset (SEU)
Single event upsets
triple modular redundancy (TMR)
Tunneling magnetoresistance
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Description
Summary:A modification of the Muller C-Element is proposed as a single event transient (SET) and single event upset (SEU) mitigation circuit. Proton tests suggests its efficiency compared to unmitigated designs.
DOI:10.1109/RADECS.2016.8093150