Virtual de-embedding study for the accurate extraction of Fin FET gate resistance

• Published in: Proceedings of the IEEE 2014 Custom Integrated Circuits Conference pp. 1 - 4
• Main Authors: Warnock, Shireen, Groves, Rob, Hongmei Li, Wachnik, Richard, Kotecha, Pooja, Sungjae Lee, Ning Lu, Solomon, Paul, Jenkins, Keith
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2014
• Subjects: Accuracy; calibration; Capacitance; De-embedding; Electrical resistance measurement; Field effect transistors; Fin FET; gate resistance; high frequency; Logic gates; on-wafer; parameter extraction; Resistance; S-parameter
• ISSN: 0886-5930; 2152-3630
• DOI: 10.1109/CICC.2014.6946026

Accurate measurement of FET gate resistance is needed to support technology development and to understand its impact on RF performance. This is especially true for high-K Metal Gate Fin FET technologies. Decreasing gate capacitance with each successive technology node has made gate resistance measurement increasingly difficult. This work presents a "Virtual De-Embedding" approach to the optimization of gate resistance measurement structures and de-embedding methodologies. This optimization was done without needing to fabricate multiple test structure variations to determine the optimal structure. We examine the effects of back-end-of-line (BEOL) stack, groundplane design, FET size, and de-embedding technique on gate resistance measurement accuracy.