Modified DEC BCH codes for parallel correction of 3-bit errors comprising a pair of adjacent errors

• Published in: 2014 IEEE 20th International On-Line Testing Symposium (IOLTS) pp. 116 - 121
• Main Authors: Badack, Christian, Kern, Thomas, Gössel, Michael
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-07-2014
• Subjects: Decoding; Error correction; Error correction codes; Polynomials; Testing; Vectors
• ISSN: 1942-9398; 1942-9401
• DOI: 10.1109/IOLTS.2014.6873682

In this paper we propose a modification of double error correcting (DEC) BCH codes that allows for a fast correction of arbitrary 1-bit and 2-bit errors, as well as 3-bit errors comprising adjacent 2-bit errors in certain bit positions. The proposed code has the same number of check bits as a double error correcting, triple error detecting (DEC-TED) BCH code with code distance 6. The proposed code is particularly useful for multi-level memories capable of storing more than one bit of data per memory cell. A method for decoding and a parallel implementation of the codes is described. Experimentally the decoding latency and area consumption is compared to parallel implementations of Hsiao SEC-DED codes, DEC BCH codes and TEC BCH codes for data bit sizes ranging from 8 to 1024 bits commonly used in memory applications.