Redundancy architectures for channel-based 3D DRAM yield improvement

• Published in: 2014 International Test Conference pp. 1 - 7
• Main Authors: Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Lee, Mincent, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-10-2014
• Subjects: 3D RAM; Built-in self-test; memory testing; Random access memory; Redundancy; redundancy analysis (RA); redundancy repair; Three-dimensional displays; Through-silicon vias; yield improvement
• ISSN: 1089-3539; 2378-2250
• DOI: 10.1109/TEST.2014.7035331

The three-dimensional integrated circuit (3D IC) is considered a promising approach that can obtain high data band-width and low power consumption for future electronic systems that require high integration level. One of the popular drivers for 3D IC is the integration of a memory stack and a logic die. Because the yield of a 3D IC is the product of respective yields of the mounted dies, the yields of the memory dies and logic die must be high enough, or the 3D IC will be too expensive to be manufactured. To obtain a high yield of 3D ICs, efficient test and repair methodologies for memories are necessary. In this paper, we target the channel-based 3D dynamic random access memory (DRAM) and propose two 3D redundancy architectures, i.e., Cubical Redundancy Architectures 1 and 2 (CRA1 and CRA2). We use Wide-IO DRAM as an example for discussion. In CRA1, spares are associated with each DRAM die as in a conventional 2D architecture. In CRA2, we use a static random access memory (SRAM) on the logic die as spares. Experimental results show that the CRA1 can achieve up to 18% higher stack yield than traditional redundancy architecture with the same area overhead. On the other hand, the CRA2 can achieve the same yield as the CRA1 with 40% less spares, but 1.3% higher area overhead.