Mitigating TSV-induced substrate noise coupling in 3-D IC using buried interface contacts

• Published in: 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems pp. 75 - 78
• Main Authors: Xiaoxiong Gu, Silberman, J., Yong Liu, Xiaomin Duan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-10-2012
• Subjects: 3-D integrated circuit (IC); 3-D integration; Capacitance; Couplings; Integrated circuit modeling; Noise; Silicon; substrate noise; Substrates; through silicon via (TSV); Through-silicon vias
• ISBN: 9781467325394; 1467325392
• ISSN: 2165-4107
• DOI: 10.1109/EPEPS.2012.6457846

Substrate noise coupling induced by Through Silicon Vias in SOI substrates is modeled and analyzed in frequency- and time-domain. In addition to a buried oxide layer, a highly doped N+ epi layer used for deep trench devices is taken into account in full-wave electromagnetic simulations. Equivalent circuit models are extracted to assess the impact of noise coupling on active circuit performance. A noise mitigation technique of using CMOS process compatible buried interface contacts is proposed and studied. Simulation results demonstrate that a low impedance ground return path can be readily created for effective substrate noise reduction in 3D IC design.