A novel low-power high-speed programmable dual modulus divider for PLL-based frequency synthesizer

• Published in: ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575) pp. 77 - 81
• Main Authors: Sulaiman, M.S., Khan, N.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2002
• Subjects: Circuit synthesis; Clocks; CMOS process; CMOS technology; Counting circuits; Digital systems; Frequency conversion; Frequency synthesizers; Power dissipation; Wireless communication
• ISBN: 9780780375789; 0780375785
• DOI: 10.1109/SMELEC.2002.1217779

A low-power high-speed programmable dual modulus divider architecture is presented. The circuit's three building blocks: prescaler, 2- and 5-bit programmable dividers; were designed using high-performance single-phase clocking latch-up circuits rather than the conventional latch-up circuits widely used in digital systems. The dividers operate based on the modulus control and parallel loading concepts, capable of operating within the division ratio of 32-127. The programmable dual-modulus divider with 2.4 GHz maximum operating frequency was designed using the 0.18-/spl mu/m CMOS technology. Post parasitics-extracted layout results verify that the total power dissipation was 2.3 mW (at 2.4 GHz, 1.8 V).