Design-technology interaction for post-32 nm node CMOS technologies

• Published in: 2010 Symposium on VLSI Technology pp. 143 - 144
• Main Author: Shahidi, G G
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-06-2010
• Subjects: Cooling; Immune system; Lithography; Logic gates; Materials; Metallization; Performance evaluation
• ISBN: 9781424454518; 1424454514
• ISSN: 0743-1562
• DOI: 10.1109/VLSIT.2010.5556204

This paper will review the technology features in the recent and upcoming nodes and how they will impact circuit design, product performance, and migratability. It will cover the challenges and serious limitations that we will face in FEOL (increased leakage, loss of body effect), BEOL (RC, electro-migration), lithography (ever more complex design rules), and power management (end of frequency scaling, very high device count). We will talk about some possible technology solutions that will address some of the above challenges (disruptive device technologies, increased number of BEOL levels, and migration to lower voltages). Net is that scaling is expected to continue to 11 nm (at least). Design is expected to become significantly more complex.