Improving SER Immunity of Combinational Logic Using Combinations of Spatial and Temporal Checking

• Published in: 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools pp. 535 - 541
• Main Authors: Tsau-Shuan Wu, Alkan, C., Chen, T.W.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2008
• Subjects: Capacitance; Combinational circuits; Combinational Logic; Costs; Integrated circuit reliability; Large scale integration; Latches; Logic devices; Parity check codes; Reliability; Soft Error; Soft Error Rate; Very large scale integration; Voltage
• ISBN: 9780769532776; 0769532772
• DOI: 10.1109/DSD.2008.82

Radiation-induced soft errors on large-scale integrated circuits are becoming increasingly problematic as device sizes are scaled down, operating voltages are reduced, and node capacitances shrink. Therefore, chip reliability has become a big issue in modern VLSI design and the importance of detecting soft error in combinational logic circuits has been recognized. In this paper a method incorporating two error detecting methods, parity check and shadow latch, is presented. The results show that the proposed method combines the best of both previously proposed methods and achieves the soft error rate reduction of 70% with 50% cost overhead for random logic blocks, providing a better cost return for using either method along.