Live demonstration: Packet-based AER with 3Gevent/s cumulative throughput

• Published in: 2011 IEEE International Symposium of Circuits and Systems (ISCAS) p. 1988
• Main Authors: Schiefer, S., Hartmann, S., Scholze, S., Partzsch, J., Mayr, C., Henker, S., Schuffny, R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2011
• Subjects: Biology; Delay; Field programmable gate arrays; Neuromorphics; Semiconductor device modeling; Throughput
• ISBN: 1424494737; 9781424494736
• ISSN: 0271-4302; 2158-1525
• DOI: 10.1109/ISCAS.2011.5937981

Traditionally, the communication in neuromorphic VLSI systems has been done via parallel asynchronous transmission of Address-Event-Representations (AER) of neuron pulses. Recently, there has been a move towards greater event transmission speed via a serialization of the AER protocols. We give a live demonstration of a packet based synchronous serial AER infrastructure presented in a recent paper, which handles the complete off-wafer communication and configuration for a newly developed waferscale neuromorphic system, operating at a factor of 10 4 faster than biological real-time. Pulse packets are routed from the host PC via Gbit Ethernet to an FPGA board, which forwards them to 4 purpose designed Digital Network ASICs (DNCs) on the same board. The DNCs buffer and sort the pulses, implementing 32 2GBit/s Low Voltage Differential Signaling (LVDS) interfaces to the neuromorphic circuits on the wafer. Pulse communication to other wafers is done via an FPGA- FPGA communication using 10 Gbit/s Aurora links.