Terminating load dependent width optimization of global inductive VLSI interconnects

• Published in: Proceedings of the IEEE Symposium on Emerging Technologies, 2005 pp. 301 - 305
• Main Authors: Kaushik, B.K., Sarkar, S., Agarwal, R.P.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Clocks; Delay; Driver circuits; Integrated circuit interconnections; Power system transients; RLC circuits; Semiconductor device modeling; Transistors; Very large scale integration; Wires
• ISBN: 0780392477; 9780780392472
• DOI: 10.1109/ICET.2005.1558898

In this paper interconnect width is optimized for a matched condition to reduce power and delay parameters. Width optimization is done for two sets of interconnect terminating conditions viz, 1) by active gate, and 2) by passive capacitance. For a driver interconnect load model terminated by an active gate, a tradeoff exists between short circuit and dynamic power in inductive interconnects, since with wider lines dynamic power increases, but short circuit power of the load gate decreases due to reduced transient delay. Whereas, for a line terminated by a capacitor, such tradeoff does not exist. The power consumption continues to increase even with reduced transient delay for wider lines. Many of the previous researches have modeled the active gate load at terminating end by its input parasitic gate capacitance. This paper shows that such modeling leads to inaccuracy in estimation of power, and therefore non-optimal width selection, especially for large fan-out conditions.