Impact of additional LDD rapid thermal annealing on submicron n-MOSFETs

• Published in: Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI pp. 234 - 237
• Main Authors: Qian Wensheng, Leong, V.K.W., Wang Yuwen, Li Yisuo, Pandey Shesh Mani, Manju, S., Benistant, F., Chu, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2003
• Subjects: Etching; Fluctuations; Implants; Impurities; MOS devices; MOSFET circuits; Rapid thermal annealing; Threshold voltage; Voltage measurement; Wood industry
• ISBN: 0780376811; 0780376730; 9780780376731; 9780780376816
• ISSN: 1078-8743; 2376-6697
• DOI: 10.1109/ASMC.2003.1194498

An additional NLDD Rapid Thermal Annealing (RTA) had been implemented in thin-gate and thick-gate NMOS transistors. The threshold voltage (Vt) distribution at different gate lengths was investigated for devices with and without NLDD RTA. Lower roll-up and roll-off of Vt was observed with the inclusion of NLDD RTA. However, this observation only occurred for phosphorus-LDD NMOS devices rather than arsenic-LDD NMOS devices. Based on experimental results, TCAD tools was applied to analyze the removal of implant-induced damages by LDD RTA and to investigate the difference in channel profiles before and after LDD RTA. Finally, the mechanism of less Reverse Short Channel Effect and Short Channel Effect with LDD RTA was presented through TCAD simulation results.