New approaches for synthesis of redundant combinatorial logic for selective fault tolerance

• Published in: 2014 IEEE 20th International On-Line Testing Symposium (IOLTS) pp. 62 - 68
• Main Authors: Hao Xie, Li Chen, Rui Liu, Evans, Adrian, Alexandrescu, Dan, Shi-Jie Wen, Wong, Rick
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-07-2014
• Subjects: approximate logic; Circuit faults; fault-tolerance; Integrated circuit modeling; Logic functions; Logic gates; logic synthesis; Mathematical model; Measurement; Vectors
• ISSN: 1942-9398; 1942-9401
• DOI: 10.1109/IOLTS.2014.6873673

With shrinking process technologies, the likelihood of mid-life faults in combinatorial logic is increasing. Approximate logic functions are a promising approach to mitigate such faults as the technique can be applied to any digital circuit, it protects against multiple fault models and offers a trade-off between increased area and fault coverage. In this paper we present a new algorithm for generating approximate logic functions. The algorithm considers the failure probabilities of the gates and it uses a sum of product (SOP) representation. The results on some circuits show that FIT rate can be reduced by 75% with an area penalty of 46% and inserting only two additional layers of logic.