FPGA implementation of fast running FIR filters

• Published in: 2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET) pp. 1282 - 1286
• Main Authors: Rengaprakash, S., Vignesh, M., Anwar, N. Syed, Pragadheesh, M., Senthilkumar, E., Sandhya, M., Manikandan, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-03-2017
• Subjects: Band-pass filters; Digital filters; Distributed Arithmetic; Fast running filters; Field programmable gate arrays; Finite impulse response filters; FIR; FPGA; Hardware; Mathematical model; Table lookup; Wireless communication
• DOI: 10.1109/WiSPNET.2017.8299970

Digital filter design using Finite Impulse Response (FIR) filters are predominantly used for various applications pertaining to digital signal processing and wireless communication. Fast running FIR filters are designed using the concepts of polyphase decomposition to provide the speed benefit. In this paper, hardware implementation of fast running FIR filter on a Virtex-5 FPGA is proposed and the design is compared with two different techniques: FIR filter design using optimized transpose structure and FIR filter design using Distributed Arithmetic (DA) approach. The fast running FIR filter designed in this paper is two times faster than the usual FIR filter.