From an analytic NBTI device model to reliability assessment of complex digital circuits

• Published in: 2014 IEEE 20th International On-Line Testing Symposium (IOLTS) pp. 19 - 24
• Main Authors: Aryan, N. Pour, Listl, A., Heiss, L., Yilmaz, C., Georgakos, G., Schmitt-Landsiedel, D.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-07-2014
• Subjects: Aging; Degradation; Integrated circuit modeling; Logic gates; Reliability; Stress; Transistors
• ISSN: 1942-9398; 1942-9401
• DOI: 10.1109/IOLTS.2014.6873666

In safety critical applications precise characterization of circuits to predict the lifetime reliability is a key challenge. This paper proposes a reliability assessment tool to model and simulate the NBTI degradation including its recovery effect during the design phase of digital circuits. The model is based on single device models and the corresponding measurement data. The circuits under test can be custom designed on transistor level and/or designed on gate level. The toolset is applied to a test circuit to evaluate its reliability within the lifetime. Considering not only the permanent component of NBTI but also the recoverable part, the tool provides a useful means to prevent an early circuit failure at minimum costs. Our studies support the applicability of the proposed method to efficiently estimate application specific reliability requirements over lifetime.