A Ka-band Dual Co-tuning Frequency Synthesizer with 21.9% Locking Range and Sub-200 fs RMS Jitter in CMOS for 5G mm-Wave Applications

• Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1 - 4
• Main Authors: Tianye He, Runxi Zhang, Hui Yang, Jiefu Wang, Chunqi Shi
• Format: Conference Proceeding
• Language: English
• Published: IEEE 27-05-2018
• Subjects: Couplings; Dual co-tuning; Frequency synthesizers; low RMS jitter; Phase locked loops; Phase noise; PLL; Transistors; Tuning; Voltage-controlled oscillators; wide LR
• ISSN: 2379-447X
• DOI: 10.1109/ISCAS.2018.8351240

This paper presents a Ka-band integer-N quadrature frequency synthesizer for 5G mm-wave communication applications. It utilizes a dual co-tuning in-phase injection-coupled quadrature voltage-controlled oscillator (IPIC-QVCO) including differential coplanar waveguide (DCPW), digitally-controlled coarse co-tuning varactor array (DCCVA), and analog-controlled fine co-tuning varactors (AFCV) and a matched injection-locked frequency divider (ILFD) to achieve wide locking range (LR), low phase noise, and small phase error. Even fabricated in low cost and large parasitic 0.13 μm CMOS, it still achieves 21.9% LR from 26.7 to 33.27 GHz, the phase noise is -114.06 dBc/Hz at 10 MHz offset from 29.832 GHz carrier, the RMS jitter is 198.8 fs, and the reference spurs are less than -51.3 dBc.