Parallel programming of a symmetric transport-triggered architecture with applications in flexible LDPC encoding

• Published in: 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) pp. 8380 - 8384
• Main Authors: Rister, Blaine, Jaaskelainen, Pekka, Silven, Olli, Hannuksela, Jari, Cavallaro, Joseph R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2014
• Subjects: Computer architecture; Encoding; Hardware; low-density parity check codes (LDPC); Open Computing Language (OpenCL); parallel computing; Parallel processing; Parity check codes; software-defined radio (SDR); Sparse matrices; transport-triggered architecture (TTA); Vectors
• ISSN: 1520-6149; 2379-190X
• DOI: 10.1109/ICASSP.2014.6855236

Exposed-datapath architectures yield small, low-power processors that trade instruction word length for aggressive compile-time scheduling and a high degree of instruction-level parallelism. In this paper, we present a general-purpose parallel accelerator consisting of a main processor and eight symmetric clusters, all in a single core. Use of a lightweight and memory-efficient application programming interface allows for the first high-performance program executing both sequential and data-parallel code on the same TTA processor. We use the processor for LDPC encoding, a popular method of forward error correction. Demonstrating the flexibility of software-defined radio, we benchmark the processor with two programs, one which can handle almost any sort of LDPC code, and another which is optimized for a specific standard. We achieve a throughput of 5 Mb/s with the flexible program and 92 Mb/s with the standard-specific one, while consuming only 95 mW at a clock frequency of 1175 MHz.