Improving interrupt handling in the nMPRA

• Published in: 2014 International Conference on Development and Application Systems (DAS) pp. 11 - 15
• Main Authors: Gaitan, Nicoleta Cristina, Gaitan, Vasile Gheorghita, Moisuc, Elena-Eugenia Ciobanu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2014
• Subjects: Computer architecture; Context; Hardware; hardware scheduler; interrupt; microprocessor; pipeline register; Pipelines; real time system; Real-time systems; Registers; Software
• DOI: 10.1109/DAAS.2014.6842419

In the most Real Time Operating Systems (RTOS), the interrupt handlers are implemented in software and they can increase the response time to external events and the overload of the CPU. Therefore, the newest RTOSs implement in hardware the interrupt handlers in order to eliminate these two problems. By analyzing traditional models for the management of interrupts, we can emphasize their inability to provide the temporal determinism required in real-time systems. This paper presents an interrupt handler implemented in hardware based on a method that uses a unified space of priorities for the tasks and interrupts, so there is not a specialized interrupt controller. This solution is integrated in the MPRA (Multi Pipeline Register Architecture) processor that contains a hardware RTOS. The major difference compared to other architectures with hardware scheduler is that the MPRA is a multi-pipeline architecture, which means that each task has its own set of pipeline registers.