Area constraint propagation in high level synthesis

• Published in: 2012 International Conference on Field-Programmable Technology pp. 247 - 252
• Main Authors: Nane, R., Sima, V. M., Bertels, K.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-12-2012
• Subjects: Algorithm design and analysis; area constraint; DWARV 2.0; Engines; FPGA; Hardware; HLS; IP networks; Kernel; Optimization; Parallel processing; unroll
• ISBN: 1467328464; 9781467328463
• DOI: 10.1109/FPT.2012.6412143

Hardware compilers which generate hardware descriptions from high-level languages are rapidly gaining in popularity. These generated descriptions are used to obtain fast implementations of software/hardware solutions in heterogeneous computing platforms. However, to obtain optimal solutions under certain platform constraints, we need intelligent hardware compilers that choose proper values for the different design parameters automatically. In this paper, we present a two-step algorithm to optimize the performance for different area constraints. The design parameters under investigation are the maximum unroll factor and the optimal allocation of resource types. Experimental results show that generated solutions are mapped into the available area at an occupancy rate between 74% and 99%. Furthermore, these solutions provide the best execution time when compared to the other solutions that satisfy the same area constraint. Finally, a reduction in design time of 42x on average can be achieved when these parameters are chosen by the compiler compared to manually selecting them.