Improvement of the fault coverage of the pseudo-random phase in column-matching BIST

• Published in: 8th Euromicro Conference on Digital System Design (DSD'05) pp. 56 - 63
• Main Authors: Fiser, P., Kubatova, H.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Built-in self-test; Circuit faults; Circuit testing; Computer science; Decoding; Fault detection; Logic design; Logic testing; Switches; Test pattern generators
• ISBN: 0769524338; 9780769524337
• DOI: 10.1109/DSD.2005.51

Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of faults should be detected by the pseudo-random phase, to reduce the number of faults to be covered in the deterministic one. We study the properties of different pseudo-random pattern generators. Their successful ness in fault covering strictly depends on the tested circuit. We examine properties of LFSRs and cellular automata. Four methods enhancing the pseudo-random fault coverage have been proposed. Then we propose a universal method to efficiently compute test weights. The observations are documented on some of the standard ISCAS benchmarks and the final BIST circuitry is synthesized using the column-matching method.