Lightweight True Random Bit Generators in PLDs: Figures of Merit and Performance Comparison

• Published in: 2019 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1 - 5
• Main Authors: Addabbo, T., Fort, A., Moretti, R., Mugnaini, M., Vignoli, V., Garcia Bosque, Miguel
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2019
• Subjects: Cryptography; Entropy; FPGA; Generators; Oscillators; Programmable logic devices; Reliability; True Random Bit Generators
• ISBN: 9781728103976; 1728103975
• ISSN: 2158-1525
• DOI: 10.1109/ISCAS.2019.8702791

We investigate and compare three low complexity circuit topologies to be implemented in programmable logic devices, for the design of True Random Bit Generators for Lightweight Cryptography. The architectures, based on the general idea of Digital Nonlinear Oscillators (DNOs), have been compared on the basis of measurement campaigns, carried out referring to figures of merit specifically introduced to assess the quality and reliability of the oscillators under test.