Efficient Characterization Methodology of Gate-Bulk Leakage and Capacitance for Ultra-Thin Oxide Partially-Depleted (PD) SOI Floating Body CMOS

• Published in: 2009 IEEE International Conference on Microelectronic Test Structures pp. 133 - 136
• Main Authors: Chen, D., Lee, R., Liu, Y.C., Guan Shyan Lin, Mao Chyuan Tang, Meng Fan Wang, Yeh, C.S., Chien, S.C.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-03-2009
• Subjects: Calibration; CMOS technology; History; Leakage current; MOSFET circuits; Parasitic capacitance; Radio frequency; Semiconductor device modeling; Space vector pulse width modulation; Testing
• ISBN: 1424442591; 9781424442591
• ISSN: 1071-9032; 2158-1029
• DOI: 10.1109/ICMTS.2009.4814626

For the first time, an efficient methodology to accurately characterize the gate-bulk leakage current (I gb ) and gate capacitance (C gg ) of PD SOI floating body (FB) devices was proposed and demonstrated in 40-nm PD SOI devices with ultra-thin oxide EOT 12 A. By applying the RF testing skill for the proposed SOI test patterns, we can eliminate properly the parasitic elements due to the co-existence opposite poly gate type the SOI T-shape body-tied (BT) device and accurately characterize and model the SOI FB I gb and C gg behaviors. Impact on the history effect was analyzed by BSIMSOI 4.0 model. History effect analysis with high pulse and low pulse width was shown. Improvement of more than 3% simulation accuracy for history effect was also demonstrated.