A multilevel fingerprinting method for FPGA IP protection

• Published in: 2013 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1789 - 1792
• Main Authors: Tingyuan Nie, Yansheng Li, Lijian Zhou, Toyonaga, Masahiko
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2013
• Subjects: Design automation; Field programmable gate arrays; Fingerprint recognition; Intellectual property; IP networks; Table lookup; Watermarking
• ISBN: 9781467357609; 146735760X
• ISSN: 0271-4302; 2158-1525
• DOI: 10.1109/ISCAS.2013.6572212

With the increasing risk of IP reuse in System on Chip (SoC) design, intellectual property (IP) techniques becomes one of the most important issues. Compare with watermarking, fingerprinting is a more effective method because is not only protects the IP owner's benefits but also user's rights. In this paper, we firstly propose a multilevel fingerprinting method for IP protection. In the typical field programmable gate array (FPGA) design flow, we first embed the watermarks into a FPGA design at netlist level by manipulating LUTs. When the IP core is compiled into a bitstream file, an individual fingerprint from IP user is then embedded into margin of FPGA. The experimental results show that the method has low resource and timing overhead, while proves a strong certificate both of IP owner and users.