Impact of TSV process on 14nm FEOL and BEOL reliability

• Published in: 2017 IEEE International Reliability Physics Symposium (IRPS) pp. 4A-2.1 - 4A-2.7
• Main Authors: Kannan, Sukeshwar, Premachandran, C. S., Smith, Daniel, Ranjan, Rakesh, Cimino, Salvatore, Kong Boon Yeap, Wu, George, Linjun Cao, Prabhu, Manjunatha, Agarwal, Rahul, Yao, Walter, England, Luke, Justison, Patrick
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-04-2017
• Subjects: characterization; Copper; Logic gates; Performance evaluation; proximity effect; reliability test; Semiconductor device reliability; Through-silicon vias; wafer thinning
• ISSN: 1938-1891
• DOI: 10.1109/IRPS.2017.7936302

This paper presents the impact of Through Silicon Via (TSV) process on wafer level reliability with respect to front-end of line (FEOL) and back-end of line (BEOL) reliability aspects. A TSV proximity study was performed by placing the TSV at various keep-out zone (KOZ) distances and different orientations of horizontal, vertical, and 45 degrees. FEOL and BEOL test structures were designed using stand-alone devices having TSV at KOZ distance of 2μm, 3μm, 5μm and 7μm and different orientations. Reliability tests show no impact on TSV KOZ on both FEOL and BEOL device performance. Additionally, we also performed a thinning study on the TSV wafers to characterize the impact of the wafer thinning process. We observed negligible difference between pre-thinning and post-thinning measurements and they fall within the expected wafer-to-wafer and lot-to-lot variability of the 14nm baseline process. As part of our ongoing reliability qualification for 14nm TSV reliability tests is currently being performed on these thin wafers.