Electrical characterization of silicided CMOS devices for embedded DRAM and logic with Ti and TiN capping layers

• Published in: Advances in Electronic Materials and Packaging 2001 (Cat. No.01EX506) pp. 185 - 187
• Main Authors: Jong-Chae Kim, Yeong-Cheol Kim, Hwa-il Seo
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2001
• Subjects: CMOS logic circuits; Cobalt; Contacts; DRAM chips; Inverters; Logic devices; Propagation delay; Random access memory; Silicides; Tin
• ISBN: 0780371577; 9780780371576
• DOI: 10.1109/EMAP.2001.983981

Cobalt silicide has been employed for embedded DRAM (dynamic random access memory) and logic (EDL) as a contact material to improve its speed. We have investigated the influences of Ti and TiN capping layers on cobalt-silicided complementary metal-oxide-semiconductor (CMOS) device characteristics. The leakage currents of Ti capped silicided, TiN capped silicided, and nonsilicided junctions that experience the full EDL integration with normal DRAM processes for stack cell capacitors are compared. A test pattern with 99 stages of CMOS inverter chain connected in series is also used to evaluate the two capping layer materials by measuring the propagation delay time of the CMOS inverters. TiN capping layer is shown to be superior to Ti capping layer with respect to the current driving capability of pMOSFETs and the resulting propagation delay time of CMOSFETs.