An analytical model for delay and crosstalk estimation in interconnects under general switching conditions

• Published in: ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445) Vol. 2; pp. 831 - 834 vol.2
• Main Authors: Becer, M., Hajj, I.N.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2000
• Subjects: Analytical models; Coupling circuits; Crosstalk; Delay effects; Delay estimation; Integrated circuit interconnections; Parasitic capacitance; Pulse inverters; Switches; Switching circuits
• ISBN: 0780365429; 9780780365421
• DOI: 10.1109/ICECS.2000.913005

The impact of interconnect coupling, in the form of delay and crosstalk, in deep submicron integrated circuit design is increasing. In timing analysis, the delay of a critical path should include the effect of crosstalk noise due to the switching of aggressor lines. The fact that the victim and aggressor lines may or may not be switching simultaneously, and the variable strengths of the drivers driving the coupled lines bring in additional levels of complexity to the delay estimation when coupling exists. In this paper, we derive a simple analytical model that takes the effect of different driver strengths into account, to accurately estimate the delay and crosstalk of two coupled interconnect lines. The model is applicable under all switching conditions: simultaneous or nonsimultaneous; in opposite directions or in the same direction.