On the relationship among accuracy, tolerance and compensation in the deep sub-micron era

• Published in: Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) pp. 99 - 104
• Main Authors: Hill, D., Domic, A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1997
• Subjects: Application specific integrated circuits; Circuit synthesis; Delay; Hardware design languages; Logic circuits; Logic design; Physics; Production; Timing; Wire
• ISBN: 0780342836; 9780780342835
• ISSN: 1063-0988; 2164-1773
• DOI: 10.1109/ASIC.1997.616986

Historically, ASIC solutions tended to be effective because the physics and scale of most production technologies allowed circuit designers (and circuit design tools) to safely abstract physical properties: the size and performance of chips could largely be predicted based on logical structure alone. But those days are going fast, and with the advent of 500 K+ gate chips in deep sub-micron (DSM) technologies, new approaches must be found, This paper starts with some background in technology trends, and then reviews the traditional "over the wall" methodology. Section 3 then proposes a "limited loops" design flow based on estimation, floorplanning, and the effective cooperation of synthesis and gate-level placement technologies. This flow is discussed from the perspective of error in the estimation processes and the ability of subsequent steps to tolerate and compensate for the error.