Triple-chip stacked CSP

• Published in: 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070) pp. 385 - 389
• Main Authors: Fukui, Y., Yano, Y., Juso, H., Matsune, Y., Miyata, K., Narai, A., Sota, Y., Takeda, Y., Fujita, K., Kada, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2000
• Subjects: Bonding; Chip scale packaging; Flash memory; Large scale integration; Polyimides; Random access memory; Semiconductor device packaging; Substrates; Telephony; Wire
• ISBN: 9780780359086; 0780359089
• DOI: 10.1109/ECTC.2000.853182

As electronic devices, particularly cellular telephones, become more compact, lighter in weight and more functional, it is becoming necessary to decrease the number of components mounted on the substrate, decrease their mounting area, and decrease their weight. To meet this need, in April of 1998 Sharp successfully developed the stacked CSP, an ultra-compact package housing two LSIs laid one on top of the other. Now mass-produced as a combination memory device containing both flash memory and SRAM for use in cellular telephones, the stacked CSP has become the most used memory package for cellular telephones. As information services provided through cellular telephones continue to grow, the LSI system can be expected to become larger in scale and the memory devices required to have greater capacity. These will in turn require packages with even higher mounting densities. To satisfy this need, Sharp developed the Triple-Chip Stacked CSP housing three LSIs. Mass production began in August 1999.