Gate stack preparation with high-k materials in a cluster tool

• Published in: 2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203) pp. 395 - 398
• Main Authors: De Gendt, S., Heyns, M., Conard, T., Hohira, H., Richard, O., Vandervorst, W., Caymax, M., Maes, J.W., Tuominen, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2001
• Subjects: CMOS technology; Electrodes; Hafnium; High K dielectric materials; High-K gate dielectrics; Inductors; Surface contamination; Throughput; Tunneling; Zirconium
• ISBN: 0780367316; 9780780367319
• DOI: 10.1109/ISSM.2001.962998

Oxide layers of metals such as Zr and Al are possible candidates to replace SiO/sub 2/ as gate dielectric for sub-1 nm EOT (Equivalent Oxide Thickness). We discuss the use of a cluster tool featuring pre-cleaning, surface treatment, metal oxide deposition and electrode deposition modules. Contamination is found to be well within specifications. Throughput is reasonable and we indicate ways how to further improve it. We describe briefly the four modules, and give first process results. An EOT of 0.77 nm measured in a capacitor with a combined Al/sub 2/O/sub 3/, and ZrO/sub 2/ layer is presented. We discuss the importance of a cluster tool for this application based on those process results.