A method for measuring the cycle-to-cycle period jitter of high-frequency clock signals

• Published in: Proceedings 19th IEEE VLSI Test Symposium. VTS 2001 pp. 102 - 110
• Main Authors: Yamaguchi, T.J., Soma, M., Halter, D., Raina, R., Nissen, J., Ishida, M.
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 2001
• Subjects: Clocks; Electric variables measurement; Frequency estimation; Frequency measurement; Microprocessors; Phase measurement; Phase noise; Quantization; Testing; Timing jitter
• ISBN: 9780769511221; 0769511228
• DOI: 10.1109/VTS.2001.923425

This paper introduces the extended /spl Delta//spl phi/ method for measuring cycle-to-cycle period jitter in PLL outputs. The theoretical basis for this method is derived from the limited condition for the average period and analytic signal theory. Sinusoidal jitter measurements verify the relationship between cycle-to-cycle period jitter and timing jitter. To validate the method, experimental data from jitter measurements on a PowerPC/sup TM/ microprocessor is analyzed in the frequency domain. Comparisons of phase quantization errors are made between the extended /spl Delta//spl phi/ method and the conventional zero-crossing method.