VENICE: A compact vector processor for FPGA applications

VENICE: A compact vector processor for FPGA applications

This article consists of a collection of slides from the author's conference presentation on VENICE (Vector Extensions to NIOS Implemented Compactly and Elegantly), a SVP (soft vector processor) intended to accelerate computationally intensive applications implemented on an FPGA. SVPs are exclu...

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Bibliographic Details
Published in:2011 IEEE Hot Chips 23 Symposium (HCS) pp. 1 - 5
Main Authors: Severance, Aaron, Lemieux, Guy
Format: Conference Proceeding
Language:English
Published: IEEE 01-08-2011
Subjects:
Field programmable gate arrays
Parallel processing
Programming
Throughput
Vector processors
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Summary:This article consists of a collection of slides from the author's conference presentation on VENICE (Vector Extensions to NIOS Implemented Compactly and Elegantly), a SVP (soft vector processor) intended to accelerate computationally intensive applications implemented on an FPGA. SVPs are exclusively for FPGAs, targeted at the productivity gap between writing custom hardware in an HDL and writing software for a soft processor in FPGA-based applications. They provide the convenience of software programming and software compile times, and yet they can achieve over 200x speedup compared to a scalar soft processor.
DOI:10.1109/HOTCHIPS.2011.7477515