Performance evaluation of multiple lookup tables algorithms for generating CRC on an FPGA

• Published in: 2011 1st International Symposium on Access Spaces (ISAS) pp. 164 - 169
• Main Authors: Akagic, A., Amano, H.
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 01-06-2011
• Subjects: Algorithm design and analysis; Delay; Field programmable gate arrays; Optimization; Polynomials; Table lookup; Throughput
• ISBN: 1457707160; 9781457707162
• DOI: 10.1109/ISAS.2011.5960941

A compact architecture of five CRC algorithms based on multiple lookup tables approach is proposed. The focus of this paper is the tradeoff between implementation by using distributed LUTs or BRAM. Our results show that BRAM-based approach is more efficient in terms of area utilization, but LUT based approach allows higher throughput. The proposed architecture has been implemented on Xilinx Virtex 6 LX195T prototyping device, requiring less than 1% of the device resources. Experimental results show that throughput doubles when number of processed bits is doubled. Maximum achieved throughput is 170 Gbps for processing 512 bits at a time with LUT-based approach. We show that in terms of achievable clock speed BRAM-based approach is more efficient when processing 32, 64 and 128 bits at a time, while higher throughput is achieved by LUT-based approach for algorithms that process 256 and 512 bits at a time. In terms of hardware cost, BRAM-based approach without register balancing optimization proved to be most efficient solution.