Design and Implementation of Optimized Register File for Streaming Applications

• Published in: 2021 25th International Symposium on VLSI Design and Test (VDAT) pp. 1 - 4
• Main Authors: Patan, Ayazulla Khan, Stathis, Dimitrios, Dhilleswararao, Pudi, Yang, Yu, Boppu, Srinivas, Hemani, Ahmed
• Format: Conference Proceeding
• Language: English
• Published: IEEE 16-09-2021
• Subjects: Energy efficiency; Hardware Accelerators; Latches; Libraries; Parallel processing; Power demand; Processor Arrays; Reconfigurable Architectures; Register File; Registers; Very large scale integration
• DOI: 10.1109/VDAT53777.2021.9600984

The increased demand for energy-efficient solutions compels system architects to explore the opportunities for minimizing area and power in the critical parts of a system. The register file is one such essential and critical component of any processor system that provides local storage for computing hardware such as arithmetic and logical unit. In this paper, we present an optimized design and implementation of a synthesizable register file that reduces the area and power consumption over an existing design. The proposed design is functionally equivalent to the existing design and uses latches in its core as main storage elements as opposed to the flip-flops; thus, reducing the area and power consumption. The proposed design has 10% less area and 23% less leakage power than the existing design when synthesized using a CMOS 45nm process libraries. Furthermore, the back-end implementation results show that the proposed design has 13% less core utilization and 2.3X less power.