A CMOS differential logic for low-power and high-speed applications

• Published in: ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196) Vol. 4; pp. 140 - 143 vol. 4
• Main Authors: Moisiadis, Y., Bouras, I., Arapoyanni, A.
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 2001
• Subjects: Clocks; CMOS logic circuits; Delay; Logic circuits; Logic design; MOS devices; Power dissipation; Recycling; Switches; Voltage
• ISBN: 9780780366855; 0780366859
• DOI: 10.1109/ISCAS.2001.922190

A new logic family called charge-sharing at precharge differential logic (CSPDL) is proposed. CSPDL utilises a charge-sharing scheme during the precharge phase. In order to equally charge the internal nodes to a voltage value lower than V/sub DD/. In this way by recycling the stored charge, the power dissipation during the precharge phase is significantly reduced. Compared to other differential logic families adopting a recycling scheme, CSPDL requires no extra biasing voltages or complicated signaling schemes. Simulations demonstrate a power reduction of 30% and a delay improvement of 57% over the conventional dynamic DCVS logic.