A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW single-channel SAR ADC in 28nm bulk CMOS

• Published in: ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference pp. 167 - 170
• Main Authors: Ramkaj, Athanasios, Strackx, Maarten, Steyaert, Michiel, Tavernier, Filip
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2017
• Subjects: bootstrapped input switch; Capacitance; capacitive DAC (CDAC); Complexity theory; Delays; dynamic comparator; high bandwidth; high sampling rate; Linearity; low power; Successive approximation register; Switches; Switching circuits
• DOI: 10.1109/ESSCIRC.2017.8094552

A 1.25GS/s 7b single-channel SAR ADC is presented with an SNDR/SFDR of 41.4dB/51dB at low frequencies, while the SNDR/SFDR at Nyquist are 40.1dB/52dB and remain still 36.4dB/50.1dB at 5GHz. The high input frequency linearity is enabled by a fast bootstrap circuit for the input switch, while the high sampling rate, the highest among recently published >34dB SNDR single-channel SAR ADCs is achieved by a Triple-Tail dynamic comparator and a Unit-Switch-Plus-Cap (USPC) DAC. The prototype ADC in 28nm CMOS consumes only 3.56mW from a 1V supply, leading to a Walden FoM of 34.4fJ/conv-step at Nyquist for a core chip area of 0.0071mm 2 .