Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS

• Published in: 2002 IEEE International SOI Conference pp. 17 - 19
• Main Authors: KIM, Keunwoo, CHUANG, Ching-Te, RIM, Kern, JOSHI, Rajiv V
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2002
• Subjects: Applied sciences; CMOS digital integrated circuits; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuit modeling; Integrated circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon on insulator technology; Stress; Performance evaluation; Silicon on insulator technology; Dielectric materials; Complementary MOS technology; Integrated circuit
• ISBN: 9780780374393; 0780374398
• DOI: 10.1109/SOI.2002.1044399

Strained-Si channel devices have recently become of interest for future high-performance applications due to higher carrier mobility and preservation of conventional device structure/geometry. One important feature in the strained-Si devices is the heterostructural band offset in the channel and buffer layer, which reduces V/sub t/, thereby increasing I/sub off/. We assess the circuit performance of strained-Si devices including SSOI via a physics-based circuit model calibrated against fabricated 70 nm strained and unstrained (control) devices. Device design point and performance projection and trade-off are presented, thus allowing exploitation of maximum performance in the strained-Si devices.