A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore

• Published in: 2022 19th International SoC Design Conference (ISOCC) pp. 79 - 80
• Main Authors: Serrano, Ronaldo, Sarmiento, Marco, Duran, Ckristian, Hoang, Trong-Thuc, Pham, Cong-Kha
• Format: Conference Proceeding
• Language: English
• Published: IEEE 19-10-2022
• Subjects: ChaCha20; Ciphers; CMOS technology; Computer networks; Encryption; Hardware; Hardware Efficiency; Power demand; Resistance; RISC-V
• DOI: 10.1109/ISOCC56007.2022.10031398

In the last decade, the efforts to provide a secure channel for end-to-end communications have focused on developing high-throughput, side-channel resistant, and hardware efficiency implementations in the Advanced Encryption Standard (AES). However, the relevance of the ChaCha20 cipher increases due to the addition in Transport Layer Security 1.3, generating another solution different than AES to provide a secure channel in end-to-end communications in computer networks. This paper shows the hardware efficiency perspective on the ChaCha20 cipher. The ChaCha20 is implemented in a \mathbf{0.18}\mu m standard CMOS technology, occupying a 25.05-kGE. In addition, the implementation reports a \mathbf{67.17}-mW and 145-Kbps/GE of power consumption and hardware efficiency, respectively. The ChaCha20 implementation increased 40% of hardware efficiency compared with the related works.