Potentials of a SiC Fan-out Wafer Level Package for High Power Application

• Published in: 2022 IEEE 9th Electronics System-Integration Technology Conference (ESTC) pp. 45 - 48
• Main Authors: Mackowiak, Piotr, Wittler, Olaf, Braun, Tanja, Conrad, Janine, Schiffer, Michael, Schneider-Ramelow, Martin
• Format: Conference Proceeding
• Language: English
• Published: IEEE 13-09-2022
• Subjects: Conductivity; Electric potential; Fan-out; FEM; High Temperature; Performance evaluation; Power Electronics; Semiconductor device modeling; SiC; Silicon carbide; Thermal resistance; Wafer bonding; Wide bandgap
• DOI: 10.1109/ESTC55720.2022.9939379

This paper describes the research on the development of a SiC Fan-out Wafer level Package for high power application. Electronic Packaging for High Power devices needs to address high temperature capability and a low thermal resistance, as thermal power losses impact the reliability of power devices. These in contrast trend towards higher power densities and performances. A comparison between Fan-out Packages with two different Mold compounds and a SiC Wafer Level Package was performed using FEM Simulation. The simulation shows the high potential of the SiC Fan-out package. It is shown that the thermal resistance of the package is reduced by 72%. This allows to package power devices with much higher power losses compared to mold embedded devices (x3.5). Additionally, we propose a manufacturing process for this package using wafer level back-end processes. It uses deep etching of SiC with an electroplated metal mask, wafer bonding and laser release technologies. It also introduces a SiC nanoparticle filled adhesive to improve thermal conductivity of the bond adhesive. The performed experiments show that up to 37.5wt% SiC nanoparticles could be mixed into the adhesive and spincoated with a good homogeneity on the wafer.