Scheduling for semiconductor assembly and test manufacturing enterprise

• Published in: 2015 IEEE 10th Conference on Industrial Electronics and Applications (ICIEA) pp. 891 - 896
• Main Authors: Yaoguang Hu, Jiawei Ke, Jiawei Yan, Jingqian Wen
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-06-2015
• Subjects: Assembly; genetic algorithm; Genetic algorithms; Job shop scheduling; multi-specification and small-batch; Optimization; Production planning; production scheduling; semiconductor assembly and test manufacturing
• DOI: 10.1109/ICIEA.2015.7334236

Semiconductor assembly and test manufacturing enterprise belong to the model of multi-specification and small-batch. It's a great challenge to make a production planning under uncertainty product categories and batches. Furthermore, product delivery time is very strict in the enterprise. Consequently, it's a key issue to develop a reasonable production planning to ensure the timely completion of the production tasks in the actual production environment. With the analysis of the production process, burn-in process is the common process from different production lines. Burn-in process has several different devices for the burn-in of different products. This paper focuses on the key process batch scheduling problem. The problem is formulated into Integer Linear Programming (ILP), considering the constraints of devices, production capacity and delivery time. The optimization goal of the model is to minimize the production time. Firstly, heuristics is used to solve the order batching and the batch sorting. And then the adaptable genetic algorithm is put forward to solve the ILP. The proposed method is demonstrated by an experimental case within acceptable computational time. Result analysis verifies the validity of the algorithm and implements production planning optimization.