indDG: A new compact model for common double gate MOSFET adapted to gate oxide thickness asymmetry

• Published in: 2015 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) pp. 1 - 6
• Main Authors: Kumar, Chethan, Sharan, Neha, Mahapatra, Santanu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-07-2015
• Subjects: Adaptation models; Asymmetric gate oxide thickness; Common Double Gate MOSFET; Compact Modeling; Integrated circuit modeling; Logic gates; Mathematical model; Non-Quasi Static Effects; Numerical models; Semiconductor device modeling; Silicon; Source/Drain Symmetry test
• DOI: 10.1109/CONECCT.2015.7383874

Here, we present a surface potential based compact model for common double gate MOSFET (indDG) along with implementation results. The model includes core model, intrinsic model (Short Geometry effects and Non-quasi static effect) and noise model for asymmetric common double gate (CDG) MOSFET. The existing models for CDG MOSFET are developed for device with symmetric oxide thickness across both the channels. However, in this model we have focused on developing a model for device with asymmetric oxide thickness. Here, we have solved the equations for device with asymmetric oxide thickness in a physical way. Thus, keeping the complexity and computational efficiency of the model to be of the same level as that of existing model. The model has been successfully implemented in smartspice circuit simulator through its Verilog-A interface. In this work we demonstrate some results obtained from the circuit simulator and show that it is matching accurately with the simulation results. The proposed model satisfies the source-drain symmetry test and therefore, can be efficiently used for any practical circuit implementation.