An Unrolled and Pipelined Architecture for SHA2 Family of Hash Functions on FPGA

• Published in: 2023 16th International Conference on Information Security and Cryptology (ISCTürkiye) pp. 1 - 6
• Main Author: Gamgam, Onur Berkay
• Format: Conference Proceeding
• Language: English
• Published: IEEE 18-10-2023
• Subjects: Cryptographic hash function; Design methodology; Field Programmable Gate Array (FPGA); Information security; Logic gates; loop unrolling; Performance analysis; pipelined design; Registers; Secure hash algorithm (SHA2); Throughput
• DOI: 10.1109/ISCTrkiye61151.2023.10336096

Cryptographic hash function is an important part of information security due to the need of integrity verification. Message compression is the most time-consuming process in the SHA2 family of hash functions. Reducing the processing time is important in high-speed applications, and the Field Programmable Gate Array (FPGA) provides a platform that can be used for this purpose. In this paper, a high-speed message compression module is proposed using pipelining and loop unrolling design methods on FPGA. A procedure to generate a pipelined design with two unrolling levels is shown, and the resultant architecture is presented as the proposed design. As a result, the block cycle of the SHA512, consisting of 80 steps, is completed in 42 steps. Performance analysis results show that the proposed unrolled and pipelined architecture for SHA512 significantly improves throughput compared to the studies in the literature.