FPGA Implementation of Textural Feature Extractor and Distance Based Classifier for Multi Modal Biometric Pattern Recognition System Using Multi Resolution Approach

The design of biometric pattern recognition with better accuracy, high robustness and good permanence is a significant design issue in pattern recognition system. A pattern recognition system in which the biological and physiological traits of the user are employed to authenticate the users is known...

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Bibliographic Details
Published in:2023 3rd International Conference on Pervasive Computing and Social Networking (ICPCSN) pp. 1644 - 1650
Main Authors: Hariprasath, S., Santhi, M., Prabakar, T.N., Koushick, V., P, Aravind, Gunasekaran, T.
Format: Conference Proceeding
Language:English
Published: IEEE 01-06-2023
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Summary:The design of biometric pattern recognition with better accuracy, high robustness and good permanence is a significant design issue in pattern recognition system. A pattern recognition system in which the biological and physiological traits of the user are employed to authenticate the users is known as biometric pattern recognition system. Unimodal biometric systems do not have the required characteristics like solidity, circumvention and permanence. When noisy data acquired from the sensor is given as input, the uni modal biometrics system's accuracy may reduce. Besides the noisy input, less variation of parameters of input data belonging to same class may be a cause for decrease in accuracy of the system. Several such limitations may be removed by applying input data from multi biometric sources. In this work, the design of a textural feature extractor and the classifier for a bimodal biometric system is described. The bimodal biometric system is constructed by fusion of iris code vector and palmprint code vector at feature level. In iris pattern, using the gray level dependent matrix values obtained from wavelet packet decomposed sub-images, the features are extracted Using gabor kernel, features are extracted from the palmprint pattern. The feature vector is formed by the concatenation of both the features after normalization is employed. By binarisation, the binary feature vector is created Using Hamming Distance and its variant, the classifier produces the classification result. The RTL description of the Hamming Distance Classifier (HDC) is written using VHDL 2008 language, Verilog HDL, and the implementation is performed on Spartan 6 FPGA. With a speed grade of 4, the propagation delay of the critical path is 330.12 ns. The obtained delay is sufficient for implementing the classifier as an off-chip design for real-time implementation.
DOI:10.1109/ICPCSN58827.2023.00275