Development of Chip to Wafer Assembly with CuSnAg Microbump on Solder on Pad Interposer using Thermocompression and Solder Reflow

Development of Chip to Wafer Assembly with CuSnAg Microbump on Solder on Pad Interposer using Thermocompression and Solder Reflow

Chip to wafer (C2W) bonding to form interconnect is not new to the industry. However, if the bottom wafer has thick (i,e ≥ 10um) Cu RDL layers, the CTE difference between Cu RDL and silicon material of the bottom wafer creates tremendous warpage during any heating or solder reflow process. Post flip...

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Bibliographic Details
Published in:2023 IEEE 25th Electronics Packaging Technology Conference (EPTC) pp. 94 - 99
Main Authors: Keng Yuen, Jason Au, Chong, Ser Choong, Daniel, Ismael Cereno
Format: Conference Proceeding
Language:English
Published: IEEE 05-12-2023
Subjects:
Height measurement
Industries
Silicon
Silver
Size measurement
Temperature measurement
Tin
Online Access:Get full text
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Summary:Chip to wafer (C2W) bonding to form interconnect is not new to the industry. However, if the bottom wafer has thick (i,e ≥ 10um) Cu RDL layers, the CTE difference between Cu RDL and silicon material of the bottom wafer creates tremendous warpage during any heating or solder reflow process. Post flip chip bonding, this warpage causes cold joints and lead to device electrical failure. We had demonstrated good solder joint connection using thermocompression process with 50um top chip to 775um bottom wafer. The bottom wafer has 3 layers of Cu RDL (each layer its 4um in thickness) and tin silver solder on pads. A detail comparison using thermo- compression and solder reflow process to perform C2W will be explored.
DOI:10.1109/EPTC59621.2023.10457893